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quad - channel isolators with integrated dc - to - dc converter data sheet adum5401w / adum5402w / adum5403w rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features iso power integrated, isolated dc - to - dc converter qualified for automotive applications regulated 5 v or 3.3 v output up to 500 mw output power quad dc - to - 25 mbps (nrz) signal isolation channels 16 - lead soic package with 7.6 mm creepage high temperature operation: 105c high common - mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition : 2500 v rms fo r 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din en 69747 -5- 2 (vde 0884 teil 2):2003 -1 v iorm = 565 v peak applications hybrid electric battery management general description the adum5401w/adum5402w/adum5403w 1 devices are quad - channel digital isolators with iso power?, an integrated, isolated dc - to - dc converter. based on the analog devices, inc., i coupler? technology, the dc - to - dc converter provides up to 500 mw of regulated, isolated power at 5.0 v (see table 1 ). th ese devices eliminate the need for a separate, isolated dc - to - dc converter in low power, isolated d esigns. the i coupler chip scale transformer technology is used to isolate the logic signals and for the magnetic components of the dc - to - dc converter. the result is a small form factor, total isolation solution. the adum5401w -1 /adum5402w -1 /adum5403w -1 versions of the isolators provide an upgraded voltage reference to ensure proper st artup under all load conditions (see the ordering guide for more information). iso power uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet e missions standards. see the an - 0971 application note for board layout recommendations . functional block dia grams figure 1. adum5401w/adum5402w/adum5403w block diagram figure 2. adum540 1w figure 3. adum540 2w figure 4. adum540 3w table 1 . power levels input voltage (v) output voltage (v) output power (mw) 5.0 5.0 500 5.0 3.3 330 3.3 3.3 200 1 protected by u.s. patents 5,952,849; 6,873,065 ; 6,903,578 ; and 7 , 075, 329 . other patents are pending. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc rect 4 channe l i coupler core v dd1 reg gnd 1 v ia v ib /v ob v ic /v oc v od rc out gnd 1 v iso gnd iso v oa v ob /v ib v oc /v ic v id v se l gnd iso adum5401w/adum5402w/ adum5403w 08758-001 3 4 5 6 14 13 12 11 adum5401w 08758-002 v ia v ib v oa v ob v ic v oc v od v id 3 4 5 6 14 13 12 11 adum5402w 08758-003 v ia v ib v oa v ob v oc v ic v od v id 3 4 5 6 14 13 12 11 adum5403w 08758-004 v ia v ob v oa v ib v oc v ic v od v id
adum5401w/adum5402w/adum5403w data sheet rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics5 v primary input supply/5 v secondary isolated supply .......................................................... 3 ? electrical characteristics3.3 v primary input supply/3.3 v secondary isolated supply .......................................................... 5 ? electrical characteristics5 v primary input supply/3.3 v secondary isolated supply .......................................................... 7 ? package characteristics ............................................................... 9 ? regulatory approvals ................................................................... 9 ? insulation and safety-related specifications ............................ 9 ? din en 69747-5-2 (vde 0884 teil 2) insulation characteristics ............................................................................ 10 ? recommended operating conditions .................................... 10 ? absolute maximum ratings .......................................................... 11 ? esd caution ................................................................................ 11 ? pin configurations and function descriptions ......................... 12 ? truth table .................................................................................. 14 ? typical performance characteristics ........................................... 15 ? terminology .................................................................................... 18 ? applications information .............................................................. 19 ? theory of operation .................................................................. 19 ? pcb layout ................................................................................. 19 ? thermal analysis ....................................................................... 19 ? propagation delay related parameters ................................... 20 ? start-up behavior....................................................................... 20 ? emi considerations ................................................................... 20 ? dc correctness and magnetic field immunity ..................... 20 ? power consumption .................................................................. 21 ? power considerations ................................................................ 22 ? insulation lifetime ..................................................................... 22 ? v iso start-up issues .................................................................... 23 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? automotive products ................................................................. 24 ? revision history 4/13rev. c to rev. d added figure 17 and figure 18; renumbered sequentially ..... 16 added start-up behavior section ................................................ 20 change to dc correctness and magnetic field immunity section .............................................................................................. 20 changes to ordering guide .......................................................... 24 11/12rev. b to rev. c changes to ordering guide .......................................................... 23 6/12rev. a to rev. b created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 added table 1; renumbered sequentially .................................... 1 changes to table 2, table 3, and table 4 ....................................... 3 changes to endnote 3 in table 5 .................................................... 4 change to table 6 ............................................................................. 5 changes to table 9 ............................................................................ 6 change to table 10 ........................................................................... 7 changes to table 13 .......................................................................... 8 change to table 16 ........................................................................... 9 change to table 18 ......................................................................... 10 changes to table 21 ........................................................................ 12 changes to table 22 ........................................................................ 13 changes to table 23 and table 24 ................................................ 14 changes to theory of operation section.................................... 18 changes to emi considerations section .................................... 19 4/12rev. 0 to rev. a changes to general description and features sections .............. 1 changed din v vde 0884-10 (vde v 0884-10):2006-12 to din en 69747-5-2 (vde 0884 teil 2):2003-1 throughout ........ 1 added electrical characteristics3.3 v primary input supply/3.3 v secondary isolated supply section .......................... 5 added table 5, table 6, and table 7; renumbered sequentially ........................................................................................ 5 added table 8 .................................................................................... 6 added electrical characteristics5 v primary input supply/ 3.3 v secondary isolated supply section ....................................... 7 added table 9, table 10, and table 11 ............................................ 7 added table 12 .................................................................................. 8 changes to table 14 and table 15 ................................................... 9 changes to table 16 ....................................................................... 10 changes to typical performance characteristics section ........ 16 changes to v iso start-up issues section ..................................... 23 changes to ordering guide .......................................................... 24 added automotive products section .......................................... 24 1/10revision 0: initial version
data sheet adum5401w/adum5402w/adum5403w rev. d | page 3 of 24 specifications electrical character istics 5 v primary input su pply/5 v secondary i solated supply typical specifications are at t a = 25c, v dd1 = v sel = v iso = 5 v. minimum/maximum specifications apply over the entire recommend ed operation range, which is 4.5 v v dd1 , v sel , v iso 5.5 v, and ?40c t a + 105c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 2 . dc -to - dc converter static specification s parameter symbol min typ max unit test conditions /comments dc -to - dc converter supply setpoint v iso 4.7 5.0 5.4 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 50 ma, v dd1 = 4.5 v to 5.5 v load regulation v iso (load) 1 5 % i iso = 10 ma to 90 ma output ripple v iso (rip) 75 mv p-p 20 mhz bandwidth, c bo = 0.1 f || 10 f, i iso = 90 ma output noise v iso (n oise ) 200 mv p-p c bo = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz output supply current i iso (max) 100 ma v iso > 4.5 v efficiency at i iso (max) 34 % i iso = 100 ma i dd1 , no v iso load i dd1 (q) 20 35 ma i dd1 , full v iso load i dd1 (max) 290 ma table 3 . dc -to - dc converter dynamic specifications parameter symbol 25 mbps c grade unit test conditions/comments min typ max supply current i nput i dd1 adum5401 w 68 ma no v iso load adum5402 w 71 ma no v iso load adum5403 w 75 ma no v iso load available to load i iso (load) adum5401w 87 ma adum5402w 85 ma adum5403w 83 ma table 4 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications data rate 25 mbps within pwd limit propagation delay t phl , t plh 45 60 ns 50% input to 50% output pulse width distortion pwd 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 40 ns within pwd limit propagation delay skew t psk 15 ns between any two units channel matching codirectional 1 t pskcd 6 ns opposing directional 2 t pskod 15 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
adum5401w/adum5402w/adum5403w data sheet rev. d | page 4 of 24 table 5. input and output characteristics parameter symbol min typ max unit test conditions /comments dc specifications logic high input threshold 1 v ih 0.7 v iso or 0 .7 v dd1 v logic low input threshold 1 v il 0.3 v iso or 0.3 v dd 1 v logic high output voltages 2 v oh v dd 1 ? 0.3 or v iso ? 0. 3 5.0 v i ox = ?20 a, v ix = v ixh v dd 1 ? 0. 5 or v iso ? 0. 5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages 2 v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v iso s uppl ies positive going threshold v uv+ 2.7 v negative going threshold v uv ? 2.4 v hyster e sis v uvh 0.3 v input currents p er channel i i ?20 +0.01 +20 a 0 v v ix v dd1 or v iso ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 3 |cm| 25 35 kv/s v ix = v dd 1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1. 0 mbps 1 v sel is a nonstandard input that has a logic threshold of approximately 0.9 v. 2 rc out is a nonstandard output intended to interface with other iso power parts. it is not recommended for standard digital loads. 3 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0. 7 v dd1 or 0.7 v iso for a high out put or v o < 0. 3 v dd1 or 0. 3 v iso for a low out put. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
data sheet adum5401w/adum5402w/adum5403w rev. d | page 5 of 24 electrical character istics 3.3 v primary input supply/3.3 v seconda ry isolated supply typical specifications are at t a = 25 c, v dd1 = v iso = 3.3 v, v sel = gnd iso . minimum/maximum specifications apply over the entire recommended operation range , which is 3.0 v v dd1 , v sel , v iso 3.6 v, and ?40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise note d. table 6 . dc -to - dc converter static specifications parameter symbol min typ max unit test conditions/comments dc -to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 30 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 6 ma to 54 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 54 ma output noise v iso (noise) 130 mv p -p c bo = 0.1 f||10 f, i iso = 54 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz output supply current i iso (max) 60 ma v iso > 3 v efficiency at i iso (max) 33 % i iso = 60 ma i dd1 , no v iso load i dd1 (q) 14 22 ma i dd1 , full v iso load i dd1 (max) 175 ma table 7 . dc -to - dc converter dynamic specifications parameter symbol 25 mbps c grade unit test conditions/comments min typ max supply current input i dd1 adum5401 w 44 ma no v iso load adum5402 w 46 ma no v iso load adum5403w 47 ma no v iso load available to load i iso (load) adum5401 w 52 ma adum5402 w 51 ma adum5403 w 49 ma table 8 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications data rate 25 mbps within pwd limit propagation delay t phl , t plh 45 60 ns 50% input to 50% output pulse width distortion pwd 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 40 ns within pwd limit propagation delay skew t psk 45 ns between any two units channel matching codirectional 1 t pskcd 6 ns opposing directional 2 t pskod 15 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 opposing directional channel matching is the absolut e value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
adum5401w/adum5402w/adum5403w data sheet rev. d | page 6 of 24 table 9 . input and output characteristics parameter symbol min typ max unit test conditions/comments dc specifications logic high input threshold 1 v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold 1 v il 0.3 v iso or 0.3 v dd1 v logic high output voltages 2 v oh v dd1 ? 0.3 or v iso ? 0.3 3.3 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 3.1 v i ox = ?4 ma, v ix = v ixh logic low output voltages 2 v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v iso supplies positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v dd1 or v iso ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 3 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v sel is a nonstandard input that has a logic threshold of approximately 0.9 v. 2 rc out is a nonstandard output intended to in terface with other iso power parts. it is not recommended for standard digital loads . 3 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.7 v dd1 or 0.7 v iso for a high output or v o < 0.3 v dd1 or 0.3 v iso for a low output. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
data sheet adum5401w/adum5402w/adum5403w rev. d | page 7 of 24 electrical character istics 5 v primary input su pply/3.3 v secondary isolated s upply typical specifications are at t a = 25c, v dd1 = 5.0 v, v iso = 3.3 v, v sel = gnd iso . minimum/maximum specifications apply over the entire recommended operation range , which is 4.5 v v dd1 5.5 v, 3.0 v v iso 3.6 v, and ? 40c t a + 105c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise note d. table 10 . dc -to - dc converter static specifications parameter symbol min typ max unit test conditions/comments dc -to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 50 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 6 ma to 54 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 90 ma output noise v iso (noise) 130 mv p -p c bo = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz ou tput supply current i iso (max) 100 ma v iso > 3 v efficiency at i iso (max) 30 % i iso = 90 ma i dd1 , no v iso load i dd1 (q) 14 22 ma i dd1 , full v iso load i dd1 (max) 230 ma table 11 . dc -to - dc converter dynamic specifications parameter symbol 25 mbps c grade unit test conditions/comments min typ max supply current input i dd1 adum5401 w 44 ma no v iso load adum5402 w 45 ma no v iso load adum5403 w 46 ma no v iso load available to load i iso (load) adum5401 w 92 ma adum5402 w 91 ma adum5403 w 89 ma table 12 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications data rate 25 mbps within pwd limit propagation delay t phl , t plh 45 60 ns 50% input to 50% output pulse width distortion pwd 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 40 ns within pwd limit propagation delay skew t psk 15 ns between any two units channel matching codirectional 1 t pskcd 6 ns opposing directional 2 t pskod 15 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
adum5401w/adum5402w/adum5403w data sheet rev. d | page 8 of 24 table 13 . input and output characteristics parameter symbol min typ max unit test conditions/comments dc specifications logic high input threshold 1 v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold 1 v il 0.3 v iso or 0.3 v dd1 v logic high output voltages 2 v oh v dd1 ? 0.2 or v iso ? 0.2 v dd1 or v iso v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 v dd1 ? 0.2 or v iso ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages 2 v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervolt age lockout uvlo v dd1 , v iso supplies positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v dd1 or v iso ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 3 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 v sel is a nonstandard input that ha s a logic threshold of approximately 0.9 v. 2 rc out is a nonstandard output intended to interface with other iso power parts. it is not recommended for standard digital loads . 3 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.7 v dd1 or 0.7 v iso for a high output or v o < 0.3 v dd1 or 0.3 v iso for a low output. the common - mode voltage slew rates apply to both rising and falling com mon - mode voltage edges.
data sheet adum5401w/adum5402w/adum5403w rev. d | page 9 of 24 package characterist ics table 14 . thermal and isolation characteristics parameter symbol min typ max unit test conditions /comments resistance (input to output) 1 r i-o 10 12 capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4- layer board with thin traces 3 1 the device is considered a 2 - terminal device; pin 1 to pin 8 are shorted together, and pin 9 to pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the thermal analysi s section for thermal model definitions. regulatory approvals table 15 . ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din en 69747 -5-2 (vde 0 884 teil 2 ):200 3-1 single protection, 2500 v rms isolation voltage basic insulation per csa 60950 -1- 03 and iec 60950 - 1, 4 00 v rms ( 566 v peak) maximum working voltage reinforced insulation, 565 v peak file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum5401w/adum5402w/adum5403w is proof tested by applying an insulation test voltage 3000 v rms for 1 second (c urrent leakage detection limit = 10 a). 2 in accordance with din en 69747 -5- 2 (vde 0884 teil 2):2003 -1 , each adum5401w/adum5402w/adum5403w is proof tested by applying an insulation test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marking branded on the component designates din en 69747 -5- 2 (vde 0884 teil 2):2003 -1 approval. insulation and safet y- related specifications table 16 . critical safety - related dimensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1- minute duration minimum external air gap (clearance) l(i01) >8.0 mm measured from input terminals to output terminals in the seating plane of the pcb , shortest distance through air minimum external tracking (creepage) l(i02) 7. 6 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index) cti > 175 v din iec 112/vde 0303, part 1 isolation group ii ia material g roup (din vde 0110, 1/89, table 1)
adum5401w/adum5402w/adum5403w data sheet rev. d | page 10 of 24 din en 69747 -5- 2 (vde 0884 teil 2) in sulation characteris tics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by the protective circuits. the asterisk (*) marking on packages denote s din en 69747 -5- 2 (vde 0884 teil 2):2003 - 1 approval. table 17 . vde characteristics description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 565 v peak input -to - output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1059 v peak input -to- output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc 904 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 678 v peak highest allowable overvoltage transient overvoltage, t tr = 10 sec v tr 4000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 5 ) case temperature t s 150 c side 1 i dd1 current i s1 555 ma insulation resistance at t s v io = 500 v r s >10 9 figure 5 . thermal derating curve, dependence of safety limiting values on case temperature, per din en 60747 -5-2 recommended operating conditions table 18 . parameter symbol min max unit operating temperature 1 t a ?40 + 10 5 c supply voltages 2 v dd1 3.0 5.5 v 1 operation at 105c requires reduction of the maximum load current, as specified in table 19 . 2 each voltage is relative to its respective ground. 08758-005 0 100 200 300 400 500 600 0 50 10 0 15 0 20 0 ambient temperature (c) safe operating v dd1 current (ma)
data sheet adum5401w/adum5402w/adum5403w rev. d | page 11 of 24 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 19 . parameter rating storage temperature (t st ) ?55c to +150c ambient operating temperature range (t a ) ?40c to +105c supply voltages (v dd 1 , v iso ) 1 ?0.5 v to +7.0 v v iso supply current 2 t a = ?40c to +85c 100 ma t a = ?40c to +105c 60 ma input voltage (v ia , v ib , v ic , v id ) 1, 3 ?0.5 v to v ddi + 0.5 v output voltage (rc out , v oa , v ob , v oc , v od ) 1, 3 ?0.5 v to v ddo + 0.5 v average output current per data output pin 4 ?10 ma to +10 ma maximum cumulative ac hi p ot 5 min at 2500 v rms maximum cumulative dc hi pot 5 min at 3500 v dc common - mode transients 5 ? 100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground s. 2 v iso provides current for dc and dynamic loads on the v iso i/o channels. this current must be included when determining the total v iso supply current. for ambient temperatures from 85c to 105c, the maximum allowed current is reduced. 3 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 4 see figure 5 for the maximum rated current values for various temperatures. 5 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cau se latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated i n the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 20 . maximum continuous working voltage supporting 50 - year mini mum lifetime 1 parameter max unit applicable certification ac voltage bipolar waveform 424 v peak all certifications, 50 - year operation basic insulation 560 v peak working voltage per iec 60950 -1 unipolar waveform basic insulation 560 v peak working voltage per iec 60950 -1 dc voltage basic insulation 560 v peak working voltage per iec 60950 -1 1 refers to the continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more information. esd caution
adum5401w/adum5402w/adum5403w data sheet rev. d | page 12 of 24 pin configurations and function descript ions figure 6. adum540 1w pin configuration table 21. adum540 1w pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground reference for the primary side of the isolator. pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allow the adum5401w to control the regulation of the slave device. 9, 15 gnd iso ground reference for the secondary side of the isolator. pin 9 and pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v oc logic outp ut c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for external loads: 3.3 v (v sel = gnd iso ) or 5.0 v (v sel = v iso ). v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5401w top view (not to scale) 08758-006
data sheet adum5401w/adum5402w/adum5403w rev. d | page 13 of 24 figure 7. adum540 2w pin configuration table 22. adum540 2w pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground reference for the primary side of the isolator. pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allow the adum5402w to control the regulation of the slave device. 9, 15 gnd iso ground reference for the secondary side of the isolator. pin 9 and pin 15 are internally connected to each other, and it is recommended that both pins be conne cted to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for external loads: 3.3 v (v sel = gnd iso ) or 5.0 v (v sel = v iso ). v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5402w top view (not to scale) 08758-007
adum5401w/adum5402w/adum5403w data sheet rev. d | page 14 of 24 figure 8. adum540 3w pin configuration table 23. adum540 3w pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage, 3.0 v to 5.5 v. 2, 8 gnd 1 ground reference for the primary side of the isolator. pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ob logic output b. 5 v oc logic output c. 6 v od logic output d. 7 rc out regulation control output. this pin is connected to the rc in pin of a slave iso power device to allow the adum5403w to control the regulation of the slave device. 9, 15 gnd iso ground reference for the secondary side of the isolator. pin 9 and pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. 11 v id logic input d. 12 v ic logic input c. 13 v ib logic input b. 14 v oa logic output a. 16 v iso secondary supply voltage output for external loads: 3.3 v (v sel = gnd iso ) or 5.0 v (v sel = v iso ). truth table table 24 . truth table (positive logic) v sel rc out 1 v dd1 (v) v iso (v) notes high pwm 5 5 master mode, normal operation low pwm 5 3.3 master mode, normal operation low pwm 3.3 3.3 master mode, normal operation high pwm 3.3 5 this supply configuration is not recommended due to extremely poor efficiency 1 pwm refers to the regulation control signal. this signal is derived from the secondary side regulator and can be used to cont rol other iso power devices. v dd1 1 gnd 1 2 v ia 3 v ob 4 v iso 16 gnd iso 15 v oa 14 v ib 13 v oc 5 v ic 12 v od 6 v id 11 rc out 7 v se l 10 gnd 1 8 gnd iso 9 adum5403w top view (not to scale) 08758-008
data sheet adum5401w/adum5402w/adum5403w rev. d | page 15 of 24 typical performance characteristics figure 9 . typical power supply efficiency at 5 v input/5 v outp ut and 3.3 v input/3.3 v output figure 10 . typical total power dissipation vs. isolated output supply current in all supported power configurations figure 11 . typical isolated output supply current vs. input current in all supported power configurations figure 12 . typical short - circuit input current and power vs. v dd1 supply voltage figure 13 . typical v iso transient load response, 5 v output, 10% to 90% load step figure 14 . typical v iso transient load response, 3.3 v output, 10% to 90% load step 08758-009 0 5 10 15 20 25 30 35 40 0 0.02 0.04 0.06 0.08 0.10 0.12 output current (a) efficienc y (%) 3.3v input/3.3v output 5v input/3.3v output 5v input/5v output 08758-010 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.02 0.04 0.06 0.08 power dissi pa tion (w) 0.10 0.12 i iso (a) v dd1 = 5 v , v iso = 5v v dd1 = 5 v , v iso = 3.3v v dd1 = 3.3 v , v iso = 3.3v 08758-0 11 0 0.02 0.04 0.06 0.08 0.10 0.12 0 0.05 0.10 0.15 0.20 0.25 0.35 0.30 input curr ent (a) o u t p u t curr ent ( a) 3.3v i nput/3.3v o utput 5v i npu t/ 3.3v o utput 5v i npu t/ 5v o utput 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 i npu t supply voltage (v) i npu t cu rr ent (a) power (w) i dd1 power 08758-012 08758-013 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load 08758-014 output voltage (500mv/div) (100s/div) dynamic load 10% load 90% load
adum5401w/adum5402w/adum5403w data sheet rev. d | page 16 of 24 figure 15 . typical v iso = 5 v output voltage ripple at 90% load figure 16 . typical v iso = 3.3 v output voltage ripple at 90% load figure 17 . typical output voltage start - up transient at 10% and 90% load, v iso = 5 v figure 18 . typical output voltage start - up transient at 10% and 90% load, v iso = 3.3 v figure 19 . typical i ch supply current per forward data channel (15 pf output load) figure 20 . typical i ch supply current per reverse da ta channel (15 pf output load) 08758-015 bw = 20mhz (400ns/div) 5v output ripple (10mv/div) data rate (mbps) 08758-016 bw = 20 mhz ( 400 ns/div) 3.3v o utput ripple ( 10m v/div) 08758-030 time (ms) v iso (v) 7 6 5 4 3 2 1 0 ?1 0 1 2 3 90% load 10% load 08758-031 time (ms) v iso (v) 5 4 3 2 1 0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 90% load 10% load 0 4 8 12 16 20 0 5 10 15 data rate (m bp s) supply curr ent (ma) 20 25 5v i nput/5v o utput 3.3v i nput/3.3v o utput 5v i nput/3.3v o utput 08758-017 08758-120 0 4 8 12 16 20 0 5 10 15 data rate (m bp s) supply curr ent ( ma) 20 25 5v i nput/5v o utput 3.3v i nput/3.3v o utput 5v i nput/3.3v o utput
data sheet adum5401w/adum5402w/adum5403w rev. d | page 17 of 24 figure 21 . typical i iso (d) dynamic supply current per input figure 22 . typical i iso ( d) dynamic supply current per output (15 pf output load) 5 0 1 2 3 4 0 5 10 15 20 25 supply current (ma) data rate (mbps) 08758-121 5v 3.3v 0 1.0 0.5 1.5 2.0 2.5 3.0 0 5 10 15 data rate (m bp s) supply curr ent (ma) 20 25 5v 3.3v 0 8758 -1 22
adum5401w/adum5402w/adum5403w data sheet rev. d | page 18 of 24 terminology i dd1 (q) i dd1 (q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operating below 2 mbps, requiring no additional dynamic supply current. i dd1 (q) reflects the minimum current operating condition. i dd1 (d) i dd1 (d) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum d ynamic load conditions. resistive loads on the outputs should be treated separately from the dynamic load. i dd1 (max) i dd1 (max) is the input current under full dynamic and v iso load conditions. i iso (load) i iso (load) is the current available to an exter nal v iso load. t phl propagation delay t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. propagation delay skew (t psk ) t psk is the magnitude of the worst - case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. channel -to - channel matching (t pskcd /t pskod ) channel - to - channel matching is the absolute value of the difference in propa gation delays between the two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the f astest data rate at which the specified pulse width distortion is guaranteed.
data sheet adum5401w/adum5402w/adum5403w rev. d | page 19 of 24 applications informa tion theory of operation the dc - to - dc converter section of the adum5401w/ adum5402w/adum5403w works on principles that are common to most modern power supplies. it is a secondary side controller architecture with isolated pulse - wid th modulation (pwm) feedback. v dd1 power is supplied to an oscillating circuit th at switches current into a chip scale air core transformer. power transferred to the secondary side is rectified and regulated to either 3.3 v or 5 v. the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. the adum5401w/adum5402w/adum5403w implement undervoltage lockout (uvlo) with hysteresis on the v dd1 power input. this feature ensures that the converter does not enter oscillation due to noisy input power or slow power - on ramp rates. in the original adum540 x w devices, a minimum load current of 10 ma is recommended to ensure optimum load regulation. smaller loads can generate excess noise on chip due to short or erratic pwm pulses. excess noise generated in this way can cause data corruption in so me circumstances. this requirement has been removed in the newer adum540 xw- 1 devices, which are recommended for new designs. pcb layout the adum5401w/adum5402w/adum5403w digital isolators with 0.5 w iso p ower integrat ed dc - to - dc converters require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins ( see figure 23 ). note that a low esr bypass capacitor is required between pin 1 and pin 2 as well as between pin 15 and pin 16 , as close to the chip pads as possible. the power supply section of the adum5401w/adum5402w/ adum5403w uses a 180 mhz oscillator frequency to efficiently pass power through its chip scale transformers. in addition, normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several oper ating frequencies. noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. t hese are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 an d pin 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 and v iso . a 10 nf capacitor should be used for optimum emi emissions performance. the smaller capacitor s must have a low esr; for example, use of a n np o ceramic capacitor is advised. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. a bypass between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless both common ground pins are connected together c lose to the packag e. figure 23 . recommended printed circuit board layout in applications involving high common - mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur affects all pins equally on a given component side. failure to ensure this c an cause voltage differentials between pins, exceeding the absolute maximum ratings specified in table 19 , thereby leading to latch - up and/or permanent damage. the adum5401w/adum5402w/adum5403w are power devices that dissipate about 1 w of power when fully loaded and running at maximum speed. bec ause it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the pcb through the ground pins. if the devices are used at high ambient temperatures, provide a thermal path from the ground pins to the pcb ground plane. the board layout in figure 23 shows enlarged pads for pin 8 and pin 9. large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. multiple vias in the thermal pads can significantly reduce temperatures inside the chip. the dimensions of the expanded pads are left to the discretion of the designer and the available board space. therma l analysis the adum5401w/adum5402w/adum5403w parts consist of four internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature re flected in the ja value from table 14. the value of ja is based on measurements taken with the parts mounted on a jedec standard, 4- layer board with fine width traces and still air. under normal operating conditions, the adum5401w/adum5402w/ adum5403w devices operate at full load across the full temper - ature range without derating the output current. however, following the recommendations in the pcb layout section decreases thermal resistance to the pcb, allowing increased thermal margins in high ambient temperatures. v dd1 gnd 1 v ia v ib /v ob v iso gnd iso v oa v ob /v ib v ic /v oc v oc /v ic v od rc out v id v se l gnd 1 by p ass < 2mm gnd iso 08758-020
adum5401w/adum5402w/adum5403w data sheet rev. d | page 20 of 24 propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 24). the propagation delay to a logic low output may differ from the propagation delay to a logic high. figure 24. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum5401w/adum5402w/adum5403w component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum5401w/ adum5402w/adum5403w components operating under the same conditions. start-up behavior the adum5401w/adum5402w/adum5403w do not contain a soft start circuit. therefore, the start-up current and voltage behavior must be taken into account when designing with these devices. when power is applied to v dd1 , the input switching circuit begins to operate and draw current when the uvlo minimum voltage is reached. the switching circuit drives the maximum available power to the output until it reaches the regulation voltage where pwm control begins. the amount of current and the time required to reach regulation voltage depends on the load and the v dd1 slew rate. with a fast v dd1 slew rate (200 s or less), the peak current draws up to 100 ma/v of v dd1 . the input voltage goes high faster than the output can turn on; therefore, the peak current is propor- tional to the maximum input voltage. with a slow v dd1 slew rate (in the millisecond range), the input voltage is not changing quickly when v dd1 reaches the uvlo minimum voltage. the current surge is approximately 300 ma because v dd1 is nearly constant at the 2.7 v uvlo voltage. the behavior during startup is similar to when the device load is a short circuit; these values are consistent with the short-circuit current shown in figure 12. when starting the device for v iso = 5 v operation, do not limit the current available to the v dd1 power pin to less than 300 ma. the adum5401w/adum5402w/a dum5403w devices may not be able to drive the output to the regulation point if a current-limiting device clamps the v dd1 voltage during startup. as a result, the adum5401w/adum5402w/adum5403w devices can draw large amounts of current at low voltage for extended periods of time. the output voltage of the adum5401w/adum5402w/ adum5403w devices exhibits viso overshoot during startup. if this overshoot could potentially damage components attached to v iso , a voltage-limiting device such as a zener diode can be used to clamp the voltage. typical behavior is shown in figure 17 and figure 18. emi considerations the dc-to-dc converter sectio n of the adum5401w/adum5402w/ adum5403w components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. grounded enclosures are recom- mended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. see the an-0971 application note for board layout recommendations. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit. this situation should occur only during power-up and power-down operations. the limitation on the magnetic field immunity of the adum5401w/adum5402w/adum5403w is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the pulses at the transformer output have an amplitude of >1.0 v. the decoder has a sensing threshold of about 0.5 v, thus estab- lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). r n is the radius of the n th turn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum5401w/ adum5402w/adum5403w, and an imposed requirement that input (v ix ) output (v ox ) t plh t phl 50% 50% 08758-021
data sheet adum5401w/adum5402w/adum5403w rev. d | page 21 of 24 the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 25. figure 25 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maxi - mum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this voltage is approximately 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst - case polarity), it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum5401w/ adum5402w/adum5403w transforme rs. figure 26 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 26 , the adum5401w/ adum5402w/adum5403w are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example, a 0.5 ka current placed 5 mm away from the adum5401w/adum5402w/ adum5403w is required to affect component operation. figure 26 . maximum allowable current for various current -to- adum5401w/adum5402w/adum5403w spacings note that , in combinations of strong magnetic field and high frequency, any loops formed by pcb traces c an induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. exercise care in the layout of such traces to avoid this possibility. power consumption the v dd1 power supply input provides power to the i coupler data channels, as well as to the power converter. for this reason, the quiesc ent currents drawn by the power converter and the primary and secondary i/o channels cannot be determined separately. all of these quiescent power demands have been combined into the i dd1 (q) current, as shown in figure 27 . the total i dd1 supply current is equal to the sum of the quiescent operating current; the dynamic current, i dd1 (d) , demanded by the i/o channels; and any external i iso load. figure 27 . power consumption within th e adum5401w/adum5402w/adum5403w dynamic i/o current is consumed only when operating a channel at speeds higher than the refresh rate of f r . the dynamic current of each channel is determined by its data rate. figure 19 shows the current for a channel in the forward direction, meaning that the input is on the v dd1 side of the part ; figure 20 shows the current for a channel in the reverse direction, meaning that the input is on the v iso side of the part. both figures assume a typical 15 pf load. the following relationship allows the total i dd1 current to be calculated: i dd1 = ( i iso v iso )/( e v dd1 ) + i chn ; n = 1 to 4 (1) where: i dd1 is the total supply input current. i chn is the current drawn by a single channel determined from figure 19 or figure 20 , depending on channel direction. i iso is the current drawn by the secondary side external load. e is the power supply efficiency at 100 ma load from figure 9 at the v iso and v dd1 condition of interest. the maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. i iso (load) = i iso (max) ? i is o (d)n ; n = 1 to 4 (2) where: i iso (load) is the current available to supply an external secondary side load. i iso (max) is the maximum external secondary side load current magnetic field frequenc y (hz) 100 maximum allo w able magnetic flux densit y (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 08758-022 magnetic field frequency (hz) maximum allowable current (ka) 1k 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 08758-023 converter primary converter seconda ry primary dat a input/output 4-channe l i ddp(d) seconda ry dat a input/output 4-channe l i iso(d) i iso i dd1(q) i dd1(d) 08758-024
adum5401w/adum5402w/adum5403w data sheet rev. d | page 22 of 24 available at v iso . i iso (d)n is the dynamic load current drawn from v iso by an i nput or output channel, as shown in figure 21 and figure 22. the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the additional current must be included in the analysis of i dd1 and i iso (load) . power considerations the adum5401w/adum5402w/adum5403w power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by uvlo circuitry. below the minimum operating volta ge, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. outputs remain in a high impedance state to prevent transmission of undefined states during power - up and power - down operations. during applic ation of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. when the primary side is above the uvlo threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. the outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. the primary side oscillator also begins to operate, transferring power to the secondary power circuits. the secondary v iso voltage is below its uvlo limit at this point; the regulation control signal from the secondary is not being generated. the primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary side , until the secondary voltage rises to its regulation setpoint. this create s a large inrush current transient at v dd1 . when the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. the v dd1 current is reduced and is then proportional to the load current. the inrush current is less than the short - circuit current shown in figure 12. the duration of the in rush current depends on the v iso loading conditions and the current available at the v dd1 pin. as the secondary side converter begins to accept power from the primary, the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data is received from the correspond - ing primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. secondary side inputs sample their state and transmit it to the primary side. outputs are valid about 1 s after the secondary side becomes active. because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required. when power is removed from v dd1 , the primary side converter and coupler shut down when the uvlo lev el is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side hold the last state that they received from the primary side. either the uvlo level is reached and the outputs are placed in their high imped ance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches uvlo. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insula - tion degradation is dependent on the characteristics of the voltage waveform applied across the insulation. analog devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the adum5401w/adum5402w/ adum5403w . accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. acceleration fact ors for several operating conditions are determined, allowing calcu - lation of the time to failure at the working voltage of interest. the values shown in table 20 sum marize the peak voltages for 50 years of service life in several operating conditions. in many cases, the working voltage approved by agency testing is higher than the 50 - year service life voltage. operation at working voltages higher than the service life voltage listed leads to premature insulation failure. the insulation lifetime of the adum5401w/adum5402w/ adum5403w depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, d epending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 28, figure 29 , and figure 30 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. a 50 - year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by analog devices . in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50 - year service life. the workin g voltages listed in table 20 can be applied while maintaining the 50- year minimum lifetime, provided th at the voltage conforms to either the unipolar ac or dc voltage cases. any cross - insulation voltage waveform that does not conform to figure 29 or figure 30 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50 - year lifetime voltage value listed in table 20.
data sheet adum5401w/adum5402w/adum5403w rev. d | page 23 of 24 figure 28 . bipolar ac waveform figure 29 . dc waveform figure 30 . unipolar ac waveform v iso start -u p issues an issue with reliable startup was identified in the adum5401w/ adum 5402w/ adum 5403w components. this issue has been addressed in the adum5401w - 1/adum5402w -1 /adum5403w - 1 for the current silicon. the adum5401w - 1/adum5402w -1/ adum5403w - 1 devices are re commend ed for all new designs. the following description applies only to the original rel eased version of these devices. production of the original release of the devices is being continued for existing customers, but it is not recommended for new designs. the st art - up issue in the original release of the adum5401w/ adum5402w/adum5403w is related to initialization of the band gap voltage references on the primary (power input) and secondary (power output) sides of the iso power device and are being addressed in fut ure revisions of the silicon. for current versions of the silicon, the user must follow these design guide - lines to guarantee proper operation of the device. the band gap voltage references are vulnerable to slow power - up slew rate. the susceptibility to power - up errors is process sensitive ; therefore, not all devices display these behaviors. these recommen - dations should be implemented for all designs until the corrections are made to the silicon. the symptoms and corrective actions required for issues with the primary and secondary side startup are different. symptom the v iso output voltage restarts to an incorrect voltage between 3.4 v and 4.7 v when power is removed at v dd1 and then reapplied between 250 ms and 3 sec later. the er ror occurs only on restart ; it does not occur at initial power - up. if the part initializes incorrectly , power must be remove d for an extended time to allow internal nodes to discharge and reset. the amount of time required can be several minutes at low tem perature ; therefore, it is critical to avoid allowing the device to initialize improperly. cause the secondary side band gap reference does not initialize to the proper voltage due to a slow slew rate o n v iso after the internal nodes are precharged during the previous power cycle. the secondary side band gap sets the output voltage of the regulator. solution the slew rate of v iso is determined by the resistive and capacitive load present on the output. designs that attempt to reduce ripple by adding capacit ance to the v iso output can slow the slew rate enough to cause start - up errors. choose values for bulk capacitance based on the effective dc l oad. calculate the dc load as the resistive equivalent to the current drawn from the v iso line. determine the rang e of allowable capacitance for the v iso output from figure 31 . choose the bulk capacitance for v iso to achieve the application required ripple , unless the value is in the disallowed combinations area ; then the value must be reduced to avoid restart issues. figure 31 . maximum capacitive load for proper restart 0v ra ted pe ak vo lt age 08758-025 0v ra ted pe ak vo lt age 08758-026 0v rated pe ak voltage notes 1. the vo lt age is shown as sinusoida l for illustr a tion purposes on ly . it is meant t o represent an y vo lt age wa veform var ying between 0v and some limiting v alue. the limiting v alue can be positive or neg a tive, but the vo lt age cannot cross 0 v. 08758-027 100k 10k 1k 100 10 1 1 10 c viso ( f) 100 1k r viso ( ?) disallowed combinations 08758-028
adum5401w/adum5402w/adum5403w data sheet rev. d | page 24 of 24 outline dimensions figure 32 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimension s shown in millimeters and (inches) ordering guide model 1 , 2 , 3 notes number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range package description package option ADUM5401WCRWZ -1 3 1 25 60 6 ?40c to +105c 16 - lead soic_w rw - 16 adum5402wcrwz -1 2 2 25 60 6 ?40c to +105c 16 - lead soic_w rw - 16 adum5403wcrwz -1 1 3 25 60 6 ?40c to +105c 16 - lead soic_w rw - 16 ADUM5401WCRWZ 4 3 1 25 60 6 ?40c to +105c 16 - lead soic_w rw - 16 adum5402wcrwz 4 2 2 25 60 6 ?40c to +105c 16 - lead soic_w rw - 16 adum5403wcrwz 4 1 3 25 60 6 ?40c to +105c 16 - lead soic_w rw - 16 1 z = rohs compliant part. 2 w = qualified for automotive applications. 3 tape and reel are available. the addition of an rl suffix designates a 13 (1,000 units) tape and reel option. 4 this device is not recommended for new designs. automotive products the adum5401w/adum5402w/adum540 3 w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ fr om the commercial models; therefore, designers shou ld review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b ? 2010 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08758 -0- 4/13(d)

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